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publication number 25295 revision a amendment +3 issue date june 14, 2005 am29lv641g data sheet retired product this product has been retired and is not recommended for designs. for new and current designs, s29gl064a supersedes am29lv641g and is the factory-recommended migration path. please refer to the s29gl064a datasheet for specifications and ordering information. availability of this docu- ment is retained for reference and historical purposes only. june 2005 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these produc ts will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions.
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advance information this document contains information on a product under development at advance micro devices. the information is intended to help you evaluate this product. do not design in the product without contacting the factory. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 25295 rev: a amendment/ +3 issue date: june 14, 2005 refer to amd?s website (www.amd.com) for the latest information. am29lv641g 64 megabit (4 m x 16-bit) cmos 3.0 volt-only uniform sector flash memory with versatilei/o ? control distinctive characteristics architectural advantages single power supply operation ? 2.7 to 3.6 volt read, erase, and program operations secsi ? (secured silicon) sector region ? 128-word sector for permanent, secure identification through an 8-word random electronic serial number ? may be programmed and locked at the factory or by the customer ? accessible through a command sequence versatilei/o ? control ? device generates data output voltages and tolerates data input voltages as determined by the voltage on the v io pin manufactured on 0.18 m process technology flexible sector architecture ? one hundred twenty-eight 32 kword sectors compatibility with jedec standards ? pinout and software compatible with single-power supply flash standard package options ? 48-pin tsop and reverse tsop (lv641gh/l only) ? 63-ball fine-pitch bga (lv640gu only) ? 64-ball fortified bga (lv640gu only) minimum 1 million erase cycle guarantee per sector 20-year data retention at 125 c performance charcteristics high performance ? access time ratings as fast as 55 ns ultra low power consumption (typical values at 3.0 v, 5 mhz) ? 9 ma typical active read current ? 26 ma typical erase/program current ? 200 na typical standby mode current program and erase performance (v hh not applied to the acc input pin) ? word program time: 7 s typical ? sector erase time: 0.6 s typical for each 32 kword sector software and hardware features hardware features ? hardware reset input (reset#): resets device for new operation ? wp# input: protects first or last 32 kword sector regardless of sector protection settings (lv641gh/l only) ? acc input: accelerates programming time for higher throughput during system production software features ? program suspend & resume: read other sectors before programming operation is completed ? sector group protection: v cc -level method of preventing program or erase operations within a sector ? temporary sector group unprotect: v id -level method of changing in previously locked sectors ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices ? erase suspend/erase resume: read/program other sectors before an erase operation is complete ? data# polling and toggle bits provide erase and programming operation status ? unlock bypass program command reduces overall multiple-word programming time this product has been retired and is not recommended for designs. for new and current designs, s29gl064a supersedes am29lv641g and is the factory-recommended migration path. please refer to the s29gl064a datasheet for specifications and ordering information. availability of this document is retained for reference and historical purposes only.
5 am29lv641g june 14, 2005 advance information general description the am29lv641g are 64 mbit, 3.0 volt (3.0 v to 3.6 v) single power supply flash memory devices organized as 4,194,304 words. data appears on dq15?dq0. these devices are designed to be programmed in-sys- tem with the standard system 3.0 volt v cc supply. a 12.0 volt v pp is not required for program or erase oper- ations. the device can also be programmed in stan- dard eprom programmers. access times of 55 regulated volage and 70 ns full voltage range are available for applications where v io v cc . the am29lv641gh/l is offered in 48-pin tsop and reverse tsop packages. the am29lv640gu is offered in a 63-ball fine-pitch bga package, and a 64-ball fortified bga. to eliminate bus contention each device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 3.0 volt power supply (2.7 v to 3.6 v) for both read and write func- tions. internally generated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the command register using standard microprocessor write timing. register con- tents serve as inputs to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithm?an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. the unlock bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four. device erasure occurs by executing the erase com- mand sequence. this initiates the embedded erase algorithm?an internal algorithm that automatically preprograms the array (if it is not already pro- grammed) before executing the erase operation. dur- ing erase, the device automatically times the erase pulse widths and verifies proper cell margin. the versatilei/o? (v io ) control allows the host sys- tem to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the v io pin. this allows the device to operate in 1.8 v or 3 v system environment as required. the host system can detect whether a program or erase operation is complete by reading the dq7 (data# polling) or dq6 (toggle) status bits . after a program or erase cycle has been completed, the de- vice is ready to read array data or accept another command. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the program suspend/program resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the system micropro- cessor to read boot-up firmware from the flash mem- ory device. the device offers a standby mode as a power-saving feature. once the system places the device into the standby mode power consumption is greatly reduced. the secsi ? (secured silicon) sector provides an minimum 128-word area for code or data that can be permanently protected. once this sector is protected, no further programming or erasing within the sector can occur. the write protect (wp#) feature protects the first or last sector by asserting a logic low on the wp# pin. the protected sector will still be protected even during accelerated programming. (am29lv641gh/l only) the accelerated program (acc) feature allows the system to program the device at a much faster rate. when acc is pulled high to v hh , the device enters the unlock bypass mode, enabling the user to reduce the time needed to do the program operation. this feature is intended to increase factory throughput during sys- tem production, but may also be used in the field if de- sired. amd?s flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunnelling. the data is programmed using hot electron injection.
june 14, 2005 am29lv641g 6 advance information table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 special package handling instructions .................................... 7 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ordering information . . . . . . . . . . . . . . . . . . . . . . . 9 device bus operations . . . . . . . . . . . . . . . . . . . . . 10 table 1. device bus operations .....................................................10 versatilei/o ? (v io ) control .................................................... 10 requirements for reading array data ................................... 10 writing commands/command sequences ............................ 11 accelerated program operation ......................................................11 autoselect functions .......................................................................11 standby mode ........................................................................ 11 automatic sleep mode ........................................................... 11 reset#: hardware reset pin ............................................... 11 output disable mode .............................................................. 12 table 2. sector address table ........................................................12 autoselect mode ..................................................................... 16 table 3. autoselect codes, (high voltage method) ......................16 sector group protection and unprotection ............................. 17 table 4. sector group protection/unprotection address table .....17 write protect (wp#) ................................................................ 18 temporary sector group unprotect ....................................... 18 figure 1. temporary sector group unprotect operation................ 18 figure 2. in-system sector group protect/unprotect algorithms ... 19 secsi ? (secured silicon) sector flash memory region ....... 20 table 5. secsi sector contents ......................................................20 figure 3. secsi sector protect verify.............................................. 21 hardware data protection ...................................................... 21 low v cc write inhibit .......................................................................21 write pulse ?glitch? protection ........................................................21 logical inhibit ..................................................................................21 power-up write inhibit ....................................................................21 common flash memory interface (cfi) . . . . . . . 21 table 6. cfi query identification string .......................................... 22 table 7. system interface string..................................................... 22 table 8. device geometry definition .............................................. 22 table 9. primary vendor-specific extended query ........................ 24 command definitions . . . . . . . . . . . . . . . . . . . . . 24 reading array data ................................................................ 24 reset command ..................................................................... 25 autoselect command sequence ............................................ 25 enter secsi sector/exit secsi sector command sequence .. 25 word program command sequence ..................................... 25 unlock bypass command sequence ..............................................26 figure 4. program operation .......................................................... 26 chip erase command sequence ........................................... 26 sector erase command sequence ........................................ 27 erase suspend/erase resume commands ........................... 27 figure 5. erase operation............................................................... 28 command definitions ............................................................. 29 table 10. command definitions...................................................... 29 write operation status . . . . . . . . . . . . . . . . . . . . . 30 dq7: data# polling ................................................................. 30 figure 6. data# polling algorithm .................................................. 30 dq6: toggle bit i .................................................................... 30 figure 7. toggle bit algorithm........................................................ 31 dq2: toggle bit ii ................................................................... 32 reading toggle bits dq6/dq2 ............................................... 32 dq5: exceeded timing limits ................................................ 32 dq3: sector erase timer ....................................................... 32 table 11. write operation status ................................................... 33 absolute maximum ratings . . . . . . . . . . . . . . . . 34 figure 8. maximum negative overshoot waveform ..................... 34 figure 9. maximum positive overshoot waveform....................... 34 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . 34 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 10. i cc1 current vs. time (showing active and automatic sleep currents) ........................................... 36 figure 11. typical i cc1 vs. frequency ............................................ 36 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 12. test setup.................................................................... 37 table 12. test specifications ......................................................... 37 key to switching waveforms. . . . . . . . . . . . . . . . 37 figure 13. input waveforms and measurement levels...................................................................... 37 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38 read-only operations ........................................................... 38 figure 14. read operation timings ............................................... 38 hardware reset (reset#) .................................................... 39 figure 15. reset timings ............................................................... 39 erase and program operatio ns .............................................. 40 figure 16. program operation timings.......................................... 41 figure 17. accelerated program timing diagram.......................... 41 figure 18. chip/sector erase operation timings .......................... 42 figure 19. data# polling timings (during embedded algorithms)...................................................... 43 figure 20. toggle bit timings (during embedded algorithms)...................................................... 44 figure 21. dq2 vs. dq6................................................................. 44 temporary sector unprotect .................................................. 45 figure 22. temporary sector group unprotect timing diagram ... 45 figure 23. sector group protect and unprotect timing diagram .. 46 alternate ce# controlled eras e and program operations ..... 47 figure 24. alternate ce# controlled write (erase/program) operation timings .............................................. 48 erase and programming performance . . . . . . . 49 latchup characteristics . . . . . . . . . . . . . . . . . . . . 49 tsop & fbga pin capacitance. . . . . . . . . . . . . . 49 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 fbe063?63-ball fine-pitch ball grid array (fbga) 11 x 12 mm package ................................................. 50 laa064?64-ball fortified ball grid array (fortified bga) 13 x 11 mm package ........................................................................... 51 ts 048?48-pin standard tsop ............................................ 52 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 53
7 am29lv641g june 14, 2005 advance information product selector guide note: see ?ac characteristics? for full specifications. block diagram part number am29lv641g speed option regulated voltage range v cc = 3.0?3.6 v 55r standard voltage range v cc = 2.7?3.6 v 70 max access time (ns) 55 70 ce# access time (ns) 55 70 oe# access time (ns) 35 35 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# wp# acc ry/by# ce# oe# stb stb dq15 ? dq0 sector switches reset# data latch y-gating cell matrix address latch a21?a0 v io
june 14, 2005 am29lv641g 8 advance information connection diagrams 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 a18 a14 a13 a12 a11 a10 a9 a8 a21 a20 we# reset# acc wp# a19 a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 v io v ss dq15 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 a18 a14 a13 a12 a11 a10 a9 a8 a21 a20 we# reset# acc wp# a19 a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 v io v ss dq15 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48-pin standard tsop 48-pin reverse tsop
9 am29lv641g june 14, 2005 advance information connection diagrams c2 d2 e2 f2 g2 h2 j2 k2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 c5 d5 e5 f5 g5 h5 j5 k5 c6 d6 e6 f6 g6 h6 j6 k6 c7 d7 a7 b7 a8 b8 a1 b1 a2 e7 f7 g7 h7 j7 k7 l7 l8 m7 m8 l1 l2 m1 m2 nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc nc nc nc dq15 v ss v io a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 a21 reset# we# dq11 dq3 dq10 dq2 a20 a18 acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 * balls are shorted together via the substrate but not connected to the die. 63-ball fbga top view, balls facing down
june 14, 2005 am29lv641g 10 advance information connection diagrams b3 c3 d3 e3 f3 g3 h3 b4 c4 d4 e4 f4 g4 h4 b5 c5 d5 e5 f5 g5 h5 b6 c6 d6 e6 f6 g6 h6 b7 c7 d7 e7 f7 g7 h7 b8 c8 d8 e8 f8 g8 h8 rfu rfu rfu v ss v io rfu rfu v ss dq15 byte# a16 a15 a14 a12 dq6 dq13 dq14 dq7 a11 a10 a8 dq4 v cc dq12 dq5 a19 a21 reset# dq3 dq11 dq10 dq2 a20 a18 wp#/acc dq1 dq9 dq8 dq0 a5 a6 a17 a3 a4 a5 a6 a7 a8 rfu a13 a9 we# ry/by# a7 b2 c2 d2 e2 f2 g2 h2 v ss oe# ce# a0 a1 a2 a4 a2 a3 b1 c1 d1 e1 f1 g1 h1 rfu rfu v io rfu rfu rfu rfu a1 rfu 64-ball fortified bga top view, balls facing down special package handling instructions special handling is required for flash memory products in molded packages (tsop and bga) the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for pro- longed periods of time.
11 am29lv641g june 14, 2005 advance information pin description a21?a0 = 22 addresses inputs dq15?dq0 = 16 data inputs/outputs ce# = chip enable input oe# = output enable input we# = write enable input wp# = hardware write protect input acc = acceleration input ry/by# = ready/busy output reset# = hardware reset pin input v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v io = output buffer power v ss = device ground nc = pin not connected internally note: wp#/acc functionality is multiplexed for am29lv641gh/l devices. ry/by# available only for am29lv640gu devices. logic symbol 22 16 dq15?dq0 a21?a0 ce# oe# we# reset# acc wp# v io ry/by#
june 14, 2005 am29lv641g 12 advance information ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. am29lv641g h 55r wh i temperature range i = industrial (?40 c to +85 c) package type e = 48-pin thin small outline package (tsop) standard pinout (ts 048) f = 48-pin thin small outline package (tsop) reverse pinout (tsr048) wh = 63-ball fine-pitch ball grid array (fbga) 0.80 mm pitch, 11 x 12 mm package (fbe063) pc = 64-ball fine-pitch ball grid array (fortified bga) 1.0 mm pitch, 13 x 11 mm package (laa064) speed option see product selector guide and valid combinations sector architecture and sector write protection (wp# = 0) h = uniform sector device, highest address sector protected l = uniform sector device, lowest address sector protected device number/description am29lv641g 64 megabit (4 m x 16-bit) cmos uniform sector flash memory with versatileio ? control 3.0 volt-only read, program, and erase valid combinations for tsop and ssop packages speed/v io range am29lv641gh73, am29lv641gl73 ei, fi 70 ns v io = 2.7 v ? 3.6 v am29lv641gh53r, am29lv641gl53r 55 ns v io = 3.0 v ? 3.6 v valid combinations for fbga packages speed/ v io range order number package marking am29lv640gu53r whi l640gu53r i 55ns v io = 3.0v ? 3.6 v am29lv640gu73 l640gu73v 70 ns v io = 2.7 v ? 3.6 v am29lv640gu53r pci l640gu53n 55 ns v io = 3.0 v ? 3.6 v am29lv640gu73 l640gu73p 70 ns v io = 2.7 v ? 3.6 v marking converstion for the am29lv641gh/l/amlv640gu enhanced-v io device, the last digit of the speed indicator specifies v io range. speed grades ending in 3 (e.g. 93, 103, etc.) indicate a 3 volt v io range; speed grades ending in 8 (e.g. 98, 108, etc.) indicate a 1.8 v v io range.
13 am29lv641g june 14, 2005 advance information device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 8.5?12.5 v, v hh = 11.5?12.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are a21:a0. sector addresses are a21:a15. 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector group protection and unprotection? section. 3. all sectors are unprotected when shipped from the factory (the secsi sector may be factory protected depending on version ordered.) 4. d in or d out as required by command sequence, data polling, or sector protect algorithm (see figure 2). versatilei/o ? (v io ) control the versatilei/o (v io ) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the v io pin. this allows the device to operate in 1.8 v or 3 v system environment as required. for example, a v i/o of 1.65?1.95 volts allows for i/o at the 3 volt level, driving and receiving signals to and from other 3 v devices on the same bus. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains operation ce# oe# we# reset# acc addresses (note 2) dq15? dq0 read l l h h x a in d out write (program/erase) l h l h x a in (note 4) accelerated program l h l h v hh a in (note 4) standby v cc 0.3 v xx v cc 0.3 v h x high-z output disable l h h h x x high-z reset x x x l x x high-z sector group protect (note 2) l h l v id x sa, a6 = l, a1 = h, a0 = l (note 4) sector group unprotect (note 2) lhl v id x sa, a6 = h, a1 = h, a0 = l (note 4) temporary sector group unprotect xxx v id x a in (note 4)
june 14, 2005 am29lv641g 14 advance information enabled for read access until the command register contents are altered. see ?requirements for reading array data? for more information. refer to the ac read-only operations table for timing specifications and to figure 14 for the timing diagram. i cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facil- itate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a word, instead of four. the ?word program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 2 indicates the address space that each sector occupies. i cc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. accelerated program operation the device offers accelerated program operations through the acc function. this function is primarily in- tended to allow faster manufacturing throughput dur- ing system production. if the system asserts v hh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the acc pin returns the device to normal op- eration. note that the acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autose- lect command sequence sections for more informa- tion. standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device re- quires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. i cc3 in the dc characteristics table represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard ad- dress access timings provide new data when ad- dresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics table represents the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of re- setting the device to reading array data. when the re- set# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory.
15 am29lv641g june 14, 2005 advance information refer to the ac characteristics tables for reset# pa- rameters and to figure 15 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state. table 2. sector address table sector a21 a20 a19 a18 a17 a16 a15 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) sa0 0 0 0 0 0 0 0 000000?00ffff 000000?007fff sa1 0 0 0 0 0 0 1 010000?01ffff 008000?00ffff sa2 0 0 0 0 0 1 0 020000?02ffff 010000?017fff sa3 0 0 0 0 0 1 1 030000?03ffff 018000?01ffff sa4 0 0 0 0 1 0 0 040000?04ffff 020000?027fff sa5 0 0 0 0 1 0 1 050000?05ffff 028000?02ffff sa6 0 0 0 0 1 1 0 060000?06ffff 030000?037fff sa7 0 0 0 0 1 1 1 070000?07ffff 038000?03ffff sa8 0 0 0 1 0 0 0 080000?08ffff 040000?047fff sa9 0 0 0 1 0 0 1 090000?09ffff 048000?04ffff sa10 0 0 0 1 0 1 0 0a0000?0affff 050000?057fff sa11 0 0 0 1 0 1 1 0b0000?0bffff 058000?05ffff sa12 0 0 0 1 1 0 0 0c0000?0cffff 060000?067fff sa13 0 0 0 1 1 0 1 0d0000?0dffff 068000?06ffff sa14 0 0 0 1 1 1 0 0e0000?0effff 070000?077fff sa15 0 0 0 1 1 1 1 0f0000?0fffff 078000?07ffff sa16 0 0 1 0 0 0 0 100000?10ffff 080000?087fff sa17 0 0 1 0 0 0 1 110000?11ffff 088000?08ffff sa18 0 0 1 0 0 1 0 120000?12ffff 090000?097fff sa19 0 0 1 0 0 1 1 130000?13ffff 098000?09ffff sa20 0 0 1 0 1 0 0 140000?14ffff 0a0000?0a7fff sa21 0 0 1 0 1 0 1 150000?15ffff 0a8000?0affff sa22 0 0 1 0 1 1 0 160000?16ffff 0b0000?0b7fff sa23 0 0 1 0 1 1 1 170000?17ffff 0b8000?0bffff sa24 0 0 1 1 0 0 0 180000?18ffff 0c0000?0c7fff sa25 0 0 1 1 0 0 1 190000?19ffff 0c8000?0cffff sa26 0 0 1 1 0 1 0 1a0000?1affff 0d0000?0d7fff sa27 0 0 1 1 0 1 1 1b0000?1bffff 0d8000?0dffff sa28 0 0 1 1 1 0 0 1c0000?1cffff 0e0000?0e7fff sa29 0 0 1 1 1 0 1 1d0000?1dffff 0e8000?0effff sa30 0 0 1 1 1 1 0 1e0000?1effff 0f0000?0f7fff
june 14, 2005 am29lv641g 16 advance information sa31 0 0 1 1 1 1 1 1f0000?1fffff 0f8000?0fffff sa32 0 1 0 0 0 0 0 200000?20ffff 100000?107fff sa33 0 1 0 0 0 0 1 210000?21ffff 108000?10ffff sa34 0 1 0 0 0 1 0 220000?22ffff 110000?117fff sa35 0 1 0 0 0 1 1 230000?23ffff 118000?11ffff sa36 0 1 0 0 1 0 0 240000?24ffff 120000?127fff sa37 0 1 0 0 1 0 1 250000?25ffff 128000?12ffff sa38 0 1 0 0 1 1 0 260000?26ffff 130000?137fff sa39 0 1 0 0 1 1 1 270000?27ffff 138000?13ffff sa40 0 1 0 1 0 0 0 280000?28ffff 140000?147fff sa41 0 1 0 1 0 0 1 290000?29ffff 148000?14ffff sa42 0 1 0 1 0 1 0 2a0000?2affff 150000?157fff sa43 0 1 0 1 0 1 1 2b0000?2bffff 158000?15ffff sa44 0 1 0 1 1 0 0 2c0000?2cffff 160000?167fff sa45 0 1 0 1 1 0 1 2d0000?2dffff 168000?16ffff sa46 0 1 0 1 1 1 0 2e0000?2effff 170000?177fff sa47 0 1 0 1 1 1 1 2f0000?2fffff 178000?17ffff sa48 0 1 1 0 0 0 0 300000?30ffff 180000?187fff sa49 0 1 1 0 0 0 1 310000?31ffff 188000?18ffff sa50 0 1 1 0 0 1 0 320000?32ffff 190000?197fff sa51 0 1 1 0 0 1 1 330000?33ffff 198000?19ffff sa52 0 1 1 0 1 0 0 340000?34ffff 1a0000?1a7fff sa53 0 1 1 0 1 0 1 350000?35ffff 1a8000?1affff sa54 0 1 1 0 1 1 0 360000?36ffff 1b0000?1b7fff sa55 0 1 1 0 1 1 1 370000?37ffff 1b8000?1bffff sa56 0 1 1 1 0 0 0 380000?38ffff 1c0000?1c7fff sa57 0 1 1 1 0 0 1 390000?39ffff 1c8000?1cffff sa58 0 1 1 1 0 1 0 3a0000?3affff 1d0000?1d7fff sa59 0 1 1 1 0 1 1 3b0000?3bffff 1d8000?1dffff sa60 0 1 1 1 1 0 0 3c0000?3cffff 1e0000?1e7fff sa61 0 1 1 1 1 0 1 3d0000?3dffff 1e8000?1effff sa62 0 1 1 1 1 1 0 3e0000?3effff 1f0000?1f7fff sa63 0 1 1 1 1 1 1 3f0000?3fffff 1f8000?1fffff sa64 1 0 0 0 0 0 0 400000?40ffff 200000?207fff sa65 1 0 0 0 0 0 1 410000?41ffff 208000?20ffff table 2. sector address table (continued) sector a21 a20 a19 a18 a17 a16 a15 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
17 am29lv641g june 14, 2005 advance information sa66 1 0 0 0 0 1 0 420000?42ffff 210000?217fff sa67 1 0 0 0 0 1 1 430000?43ffff 218000?21ffff sa68 1 0 0 0 1 0 0 440000?44ffff 220000?227fff sa69 1 0 0 0 1 0 1 450000?45ffff 228000?22ffff sa70 1 0 0 0 1 1 0 460000?46ffff 230000?237fff sa71 1 0 0 0 1 1 1 470000?47ffff 238000?23ffff sa72 1 0 0 1 0 0 0 480000?48ffff 240000?247fff sa73 1 0 0 1 0 0 1 490000?49ffff 248000?24ffff sa74 1 0 0 1 0 1 0 4a0000?4affff 250000?257fff sa75 1 0 0 1 0 1 1 4b0000?4bffff 258000?25ffff sa76 1 0 0 1 1 0 0 4c0000?4cffff 260000?267fff sa77 1 0 0 1 1 0 1 4d0000?4dffff 268000?26ffff sa78 1 0 0 1 1 1 0 4e0000?4effff 270000?277fff sa79 1 0 0 1 1 1 1 4f0000?4fffff 278000?27ffff sa80 1 0 1 0 0 0 0 500000?50ffff 280000?287fff sa81 1 0 1 0 0 0 1 510000?51ffff 288000?28ffff sa82 1 0 1 0 0 1 0 520000?52ffff 290000?297fff sa83 1 0 1 0 0 1 1 530000?53ffff 298000?29ffff sa84 1 0 1 0 1 0 0 540000?54ffff 2a0000?2a7fff sa85 1 0 1 0 1 0 1 550000?55ffff 2a8000?2affff sa86 1 0 1 0 1 1 0 560000?56ffff 2b0000?2b7fff sa87 1 0 1 0 1 1 1 570000?57ffff 2b8000?2bffff sa88 1 0 1 1 0 0 0 580000?58ffff 2c0000?2c7fff sa89 1 0 1 1 0 0 1 590000?59ffff 2c8000?2cffff sa90 1 0 1 1 0 1 0 5a0000?5affff 2d0000?2d7fff sa91 1 0 1 1 0 1 1 5b0000?5bffff 2d8000?2dffff sa92 1 0 1 1 1 0 0 5c0000?5cffff 2e0000?2e7fff sa93 1 0 1 1 1 0 1 5d0000?5dffff 2e8000?2effff sa94 1 0 1 1 1 1 0 5e0000?5effff 2f0000?2f7fff sa95 1 0 1 1 1 1 1 5f0000?5fffff 2f8000?2fffff sa96 1 1 0 0 0 0 0 600000?60ffff 300000?307fff sa97 1 1 0 0 0 0 1 610000?61ffff 308000?30ffff sa98 1 1 0 0 0 1 0 620000?62ffff 310000?317fff sa99 1 1 0 0 0 1 1 630000?63ffff 318000?31ffff sa100 1 1 0 0 1 0 0 640000?64ffff 320000?327fff table 2. sector address table (continued) sector a21 a20 a19 a18 a17 a16 a15 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
june 14, 2005 am29lv641g 18 advance information note: all sectors are 32 kwords in size. sa101 1 1 0 0 1 0 1 650000?65ffff 328000?32ffff sa102 1 1 0 0 1 1 0 660000?66ffff 330000?337fff sa103 1 1 0 0 1 1 1 670000?67ffff 338000?33ffff sa104 1 1 0 1 0 0 0 680000?68ffff 340000?347fff sa105 1 1 0 1 0 0 1 690000?69ffff 348000?34ffff sa106 1 1 0 1 0 1 0 6a0000?6affff 350000?357fff sa107 1 1 0 1 0 1 1 6b0000?6bffff 358000?35ffff sa108 1 1 0 1 1 0 0 6c0000?6cffff 360000?367fff sa109 1 1 0 1 1 0 1 6d0000?6dffff 368000?36ffff sa110 1 1 0 1 1 1 0 6e0000?6effff 370000?377fff sa111 1 1 0 1 1 1 1 6f0000?6fffff 378000?37ffff sa112 1 1 1 0 0 0 0 700000?70ffff 380000?387fff sa113 1 1 1 0 0 0 1 710000?71ffff 388000?38ffff sa114 1 1 1 0 0 1 0 720000?72ffff 390000?397fff sa115 1 1 1 0 0 1 1 730000?73ffff 398000?39ffff sa116 1 1 1 0 1 0 0 740000?74ffff 3a0000?3a7fff sa117 1 1 1 0 1 0 1 750000?75ffff 3a8000?3affff sa118 1 1 1 0 1 1 0 760000?76ffff 3b0000?3b7fff sa119 1 1 1 0 1 1 1 770000?77ffff 3b8000?3bffff sa120 1 1 1 1 0 0 0 780000?78ffff 3c0000?3c7fff sa121 1 1 1 1 0 0 1 790000?79ffff 3c8000?3cffff sa122 1 1 1 1 0 1 0 7a0000?7affff 3d0000?3d7fff sa123 1 1 1 1 0 1 1 7b0000?7bffff 3d8000?3dffff sa124 1 1 1 1 1 0 0 7c0000?7cffff 3e0000?3e7fff sa125 1 1 1 1 1 0 1 7d0000?7dffff 3e8000?3effff sa126 1 1 1 1 1 1 0 7e0000?7effff 3f0000?3f7fff sa127 1 1 1 1 1 1 1 7f0000?7fffff 3f8000?3fffff table 2. sector address table (continued) sector a21 a20 a19 a18 a17 a16 a15 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
19 am29lv641g june 14, 2005 advance information autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equip- ment to automatically match a device to be pro- grammed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (8.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in table 3. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see table 2). table 3 shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corre- sponding identifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 10. this method does not require v id . refer to the autoselect com- mand sequence section for more information. table 3. autoselect codes, (high voltage method) legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. note: secsi? sector indicator bit (dq7) exist only in the am29lv641gh/l devices. description ce# oe# we# a21 to a15 a14 to a10 a9 a8 to a7 a7 to a0 a6 a5 to a2 a1 a0 dq15 to dq0 manufacturer id : amd ll h x x v id x ? l x l l xx01h autoselect device code read cycle 1 l l h x x v id x ? l x l h 22d7h read cycle 2 l l h x x v id 0eh l l h 220fh read cycle 3 l l h x x v id 0fh l l h xx00h sector protection verification ll h sa x v id x?l x h l 01h (protected), 00h (unprotected) secsi ? sector indicator bit (dq7) ll h x x v id x?l x h h 98h (factory locked), 18h (not factory locked) secsi ? sector indicator bit (dq7), wp# protects highest address sector ll h x x v id x?l x h h xx98h (factory locked), xx18h (not factory locked) secsi ? sector indicator bit (dq7), wp# protects lowest address sector ll h x x v id x?l x h h xx88h (factory locked), xx08h (not factory locked)
june 14, 2005 am29lv641g 20 advance information sector group protection and unprotection the hardware sector group protection feature disables both program and erase operations in any sector group. in this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see table 4). the hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. sector group protection/unprotection can be implemented via two methods. the primary method requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 2 shows the algo- rithms and figure 23 shows the timing diagram. this method uses standard microprocessor bus cycle tim- ing. for sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group unprotect write cycle. the alternate method intended only for programming equipment requires v id on address pin a9 and oe#. this method is compatible with programmer routines written for earlier 3.0 volt-only amd flash devices. publication number 22367 contains further details; contact an amd representative to request a copy. the device is shipped with all sector groups unpro- tected. amd offers the option of programming and protecting sector groups at its factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector group is protected or unprotected. see the autoselect mode section for details. table 4. sector group protection/unprotection address table note: all sector groups are 128 kwords in size. sector group a21?a17 sa0?sa3 00000 sa4?sa7 00001 sa8?sa11 00010 sa12?sa15 00011 sa16?sa19 00100 sa20?sa23 00101 sa24?sa27 00110 sa28?sa31 00111 sa32?sa35 01000 sa36?sa39 01001 sa40?sa43 01010 sa44?sa47 01011 sa48?sa51 01100 sa52?sa55 01101 sa56?sa59 01110 sa60?sa63 01111 sa64?sa67 10000 sa68?sa71 10001 sa72?sa75 10010 sa76?sa79 10011 sa80?sa83 10100 sa84?sa87 10101 sa88?sa91 10110 sa92?sa95 10111 sa96?sa99 11000 sa100?sa103 11001 sa104?sa107 11010 sa108?sa111 11011 sa112?sa115 11100 sa116?sa119 11101 sa120?sa123 11110 sa124?sa127 11111
21 am29lv641g june 14, 2005 advance information write protect (wp#) the write protect function provides a hardware method of protecting the first or last sector without using v id . if the system asserts v il on the wp# pin, the device disables program and erase functions in the first or last sector independently of whether those sectors were protected or unprotected using the method de- scribed in ?sector group protection and unprotection?. note that if wp# is at v il when the device is in the standby mode, the maximum input load current is in- creased. see the table in ?dc characteristics?. if the system asserts v ih on the wp# pin, the device reverts to whether the first or last sector was previ- ously set to be protected or unprotected using the method described in ?sector group protection and unprotection?. temporary sector group unprotect ( note: in this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see table 4)). this feature allows temporary unprotection of previ- ously protected sector groups to change data in-sys- tem. the sector group unprotect mode is activated by setting the reset# pin to v id (8.5 v ? 12.5 v). during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. once v id is removed from the reset# pin, all the previously protected sector groups are protected again. figure 1 shows the algorithm, and figure 22 shows the timing diagrams, for this feature. figure 1. temporary sector group unprotect operation start perform erase or program operations reset# = v ih temporary sector group unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sector groups unprotected (if wp# = v il , the first or last sector will remain protected). 2. all previously protected sector groups are protected once again.
june 14, 2005 am29lv641g 22 advance information figure 2. in-system sector group protect/unprotect algorithms sector group protect: write 60h to sector group address with a6 = 0, a1 = 1, a0 = 0 set up sector group address wait 150 s verify sector group protect: write 40h to sector group address twith a6 = 0, a1 = 1, a0 = 0 read from sector group address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector group protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector group unprotect mode no sector group unprotect: write 60h to sector group address with a6 = 1, a1 = 1, a0 = 0 set up first sector group address wait 15 ms verify sector group unprotect: write 40h to sector group address with a6 = 1, a1 = 1, a0 = 0 read from sector group address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector group verified? remove v id from reset# write reset command sector group unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector group unprotect mode no all sector groups protected? yes protect all sector groups: the indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address set up next sector group address no yes no yes no no yes no sector group protect algorithm sector group unprotect algorithm first write cycle = 60h? protect another sector group? reset plscnt = 1
23 am29lv641g june 14, 2005 advance information secsi ? (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is 128 words in length, and uses a secsi sector indicator bit (dq7) to indicate whether or not the secsi sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the secu- rity of the esn once the product is shipped to the field. amd offers the device with the secsi sector either factory locked or customer lockable. the fac- tory-locked version is always protected when shipped from the factory, and has the secsi (secured silicon) sector indicator bit permanently set to a ?1.? the cus- tomer-lockable version is shipped with the secsi sec- tor unprotected, allowing customers to utilize that sector in any manner they choose. the customer-lock- able version also has the secsi sector indicator bit permanently set to a ?0.? thus, the secsi sector indi- cator bit prevents customer-lockable devices from being used to replace devices that are factory locked. the secsi sector address space in this device is allo- cated as follows: *all uniform devices (not including uniform high) such as am29lv640gu has its sector starting at address 0. the system accesses the secsi sector through a command sequence (see ?enter secsi sector/exit secsi sector command sequence?). after the system has written the enter secsi sector command se- quence, it may read the secsi sector by using the ad- dresses normally occupied by the first sector (sa0). this mode of operation continues until the system is- sues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to sector sa0. factory locked: secsi sector programmed and protected at the factory in devices with an esn, the secsi sector is protected when the device is shipped from the factory. the secsi sector cannot be modified in any way. a factory locked device has an 8-word random esn at addresses 000000h?000007h. customers may opt to have their code programmed by amd through the amd expressflash service. the de- vices are then shipped from amd?s factory with the secsi sector permanently locked. contact an amd representative for details on using amd?s express- flash service. customer lockable: secsi sector not programmed or protected at the factory as an alternative to the factory-locked version, the de- vice may be ordered such that the customer may pro- gram and protect the 128-word secsi sector. programming and protecting the secsi sector must be used with caution since, once protected, there is no procedure available for unprotecting the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. the secsi sector area can be protected using one of the following procedures: write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, ex- cept that reset# may be at either v ih or v id . this allows in-system protection of the secsi sector without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector. write the three-cycle enter secsi sector region command sequence, and then use the alternate method of sector protection described in the ?sector group protection and unprotection? section. once the secsi sector is programmed, locked and verified, the system must write the exit secsi sector region command sequence to return to reading and writing within the remainder of the array. table 5. secsi sector contents secsi sector address range standard factory locked expressflash factory locked customer lockable 000000h?000007h esn esn or determined by customer determined by customer 000008h?00007fh unavailable determined by customer
june 14, 2005 am29lv641g 24 advance information figure 3. secsi sector protect verify hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 10 for com- mand definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the sys- tem writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 6?9. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 6?9. the system must write the reset command to return the device to reading array data. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. al- ternatively, contact an amd representative for copies of these documents. write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
25 am29lv641g june 14, 2005 advance information table 6. cfi query identification string table 7. system interface string table 8. device geometry definition addresses (x16) data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) addresses (x16) data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0003h typical timeout per single byte/word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000ah typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0005h max. timeout for byte/word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0002h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) addresses (x16) data description 27h 0017h device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0002h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100)
june 14, 2005 am29lv641g 26 advance information 31h 32h 33h 34h 007eh 0000h 0000h 0001h erase block region 2 information (refer to cfi publication 100) 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100)
27 am29lv641g june 14, 2005 advance information table 9. primary vendor-s pecific extended query command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. table 10 defines the valid register command sequences. writing incorrect address and data val- ues or writing them in the improper sequence may place the device in an unknown state. a reset com- mand is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. after completing a pro- gramming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the device is in the autoselect mode. see the next section, reset command, for more infor- mation. addresses (x16) data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0004h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 5-2) 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0004h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0004h sector protect/unprotect scheme 04 = 29lv800 mode 4ah 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 00xxh 00h = uniform sector device
june 14, 2005 am29lv641g 28 advance information see also requirements for reading array data in the device bus operations section for more information. the read-only operations table provides the read pa- rameters, and figure 14 shows the timing diagram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming be- gins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the de- vice entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. table 10 shows the address and data requirements. this method is an alternative to that shown in table 3, which is intended for prom programmers and re- quires v id on address pin a9. the autoselect com- mand sequence may be written to an address that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the de- vice is actively programming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence: a read cycle at address xx00h returns the manu- facturer code. a read cycle at address xx01h returns the device code. a read cycle to an address containing a sector group address (sa), and the address 02h on a7?a0 in word mode returns 01h if the sector group is pro- tected, or 00h if it is unprotected. (refer to table 4 for valid sector addresses). the system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in erase suspend). enter secsi sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing an 8-word random electronic serial num- ber (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector command sequence. the exit secsi sector command sequence returns the de- vice to normal operation. table 10 shows the address and data requirements for both command sequences. see also ?secsi ? (secured silicon) sector flash memory region? for further information. word program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 10 shows the address and data requirements for the word program command sequence. when the embedded program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7 or dq6. refer to the write operation status sec- tion for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed
29 am29lv641g june 14, 2005 advance information from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was suc- cessful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass pro- gram command, a0h; the second cycle contains the program address and data. additional data is pro- grammed in the same manner. this mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. table 10 shows the require- ments for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the data 90h. the second cycle must contain the data 00h. the device then returns to the read mode. the device offers accelerated program operations through the acc pin. when the system asserts v hh on the acc pin, the device automatically enters the un- lock bypass mode. the system may then write the two-cycle unlock bypass program command se- quence. the device uses the higher voltage on the acc pin to accelerate the operation. note that the acc pin must not be at v hh for operations other than accelerated programming, or device damage may re- sult. figure 4 illustrates the algorithm for the program oper- ation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 16 for timing diagrams. figure 4. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 10 shows the address and data requirements for the chip erase command sequence. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 10 for program command sequence.
june 14, 2005 am29lv641g 30 advance information when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6 or dq2. refer to the write operation status section for infor- mation on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that oc- curs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 5 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 18 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. table 10 shows the ad- dress and data requirements for the sector erase com- mand sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets the device to the read mode. the system must rewrite the command se- quence and any additional addresses and commands. the system can monitor dq3 to determine if the sec- tor erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing sector. the system can de- termine the status of the erase operation by reading dq7, dq6, or dq2 in the erasing sector. refer to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 5 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 18 section for timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written dur- ing the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a max- imum of 20 s to suspend the erase operation. how- ever, when the erase suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the device enters the erase-suspend-read mode. the sys- tem can read data from or program data to any sector not selected for erasure. (the device ?erase sus- pends? all sectors selected for erasure.) reading at any address within erase-suspended sectors pro- duces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for infor- mation on these status bits. after an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard word program operation.
31 am29lv641g june 14, 2005 advance information refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. the address of the erase-suspended sector is required when writ- ing this command. further writes of the resume com- mand are ignored. another erase suspend command can be written after the chip has resumed erasing. figure 5. erase operation start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 10 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
june 14, 2005 am29lv641g 32 advance information command definitions table 10. command definitions legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a21?a15 uniquely select any sector. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a21?a15 are don?t cares. 6. no unlock or command cycles required when device is in read mode. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when the device is in the autoselect mode, or if dq5 goes high (while the device is providing status information). 8. the fourth cycle of the autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. see the autoselect command sequence section for more information. 9. if wp# protects the highest address sector, the data is 98h for factory locked and 18h for not factory locked. if wp# protects the lowest address sector, the data is 88h for factory locked and 08h for not factor locked. 10. the data is 00h for an unprotected sector group and 01h for a protected sector group. 11. the unlock bypass command is required prior to the unlock bypass program command. 12. the unlock bypass reset command is required to return to the read mode when the device is in the unlock bypass mode. 13. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 14. the erase resume command is valid only during the erase suspend mode. 15. command is valid when device is ready to read array data or when device is in autoselect mode. 16. bottom boot = 2200 and top boot = 2201. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id 4 555 aa 2aa 55 555 90 x00 0001 device id 4 555 aa 2aa 55 555 90 x01 22e7 x0e 220f x0f (note 16) secsi ? sector factory protect (note 9) 4 555 aa 2aa 55 555 90 x03 (see note 9) sector group protect verify (note 10) 4 555 aa 2aa 55 555 90 (sa)x02 xx00/ xx01 enter secsi sector region 3 555 aa 2aa 55 555 88 exit secsi sector region 4 555 aa 2aa 55 555 90 xxx 00 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 11) 2 xxx a0 pa pd unlock bypass reset (note 12) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 13) 1 ba b0 erase resume (note 14) 1 ba 30 cfi query (note 15) 1 55 98
33 am29lv641g june 14, 2005 advance information write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 11 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is com- plete or in progress. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device out- puts on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is ac- tive for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. however, if the sys- tem reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 will appear on suc- cessive read cycles. table 11 shows the outputs for data# polling on dq7. figure 6 shows the data# polling algorithm. figure 19 in the ac characteristics section shows the data# polling timing diagram. figure 6. data# polling algorithm dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or com- plete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any ad- dress, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a secto r erase operation, a valid address is any sector addres s within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? becaus e dq7 may change simultaneously with dq5.
june 14, 2005 am29lv641g 34 advance information program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approxi- mately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the de- vice enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alterna- tively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 11 shows the outputs for toggle bit i on dq6. figure 7 shows the toggle bit algorithm. figure 20 in the ?ac characteristics? section shows the toggle bit timing diagrams. figure 21 shows the differences be- tween dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 figure 7. toggle bit algorithm note: the system should recheck the toggle bit even if dq 5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
35 am29lv641g june 14, 2005 advance information dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce# to con- trol the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 11 to compare out- puts for dq2 and dq6. figure 7 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the dq6: toggle bit i subsection. figure 20 shows the toggle bit timing diagram. figure 21 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 7 for the following discussion. when- ever the system initially begins reading toggle bit sta- tus, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of figure 7). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if the device was previ- ously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between addi- tional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 11 shows the status of dq3 relative to the other status bits.
june 14, 2005 am29lv641g 36 advance information table 11. write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle embedded erase algorithm 0 toggle 0 1 toggle erase suspend mode erase-suspend-re ad erase suspended sector 1 no toggle 0 n/a toggle non-erase suspended sector data data data data data erase-suspend-program dq7# toggle 0 n/a n/a
37 am29lv641g june 14, 2005 advance information absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . ?65 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v v io . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +5.5 v a9 , oe#, acc, and reset# (note 2) . . . . . . . . . . . . . . . . . . . . ?0.5 v to +12.5 v all other pins (note 1) . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 8. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 9. 2. minimum dc input voltage on pins a9, oe#, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 8. maximum dc input voltage on pin a9, oe#, acc, and reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c v cc supply voltages v cc for all devices . . . . . . . . . . . . . . . . . 2.7 v to 3.6 v operating ranges define those limits between which the functionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v figure 8. maximum negative overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v figure 9. maximum positive overshoot waveform
june 14, 2005 am29lv641g 38 advance information dc characteristics cmos compatible notes: 1. on the wp# pin only, the maximum input load current when wp# = v il is 5.0 a. 2. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 3. maximum i cc specifications are tested with v cc = v cc max. 4. i cc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 6. if v io < v cc , maximum v il for ce# is 0.3 x v io . if v io < v cc , minimum v ih for ce# is 0.3 x v io . 7. not 100% tested. parameter symbol parameter description test conditions min typ max unit i li input load current (note 1) v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, acc input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (notes 2, 3) ce# = v il, oe# = v ih 5 mhz 9 16 ma 1 mhz 2 4 i cc2 v cc active write current (notes 3, 4) ce# = v il, oe# = v ih , we# = v il 15 26 ma i cc3 v cc standby current (note 3) ce#, reset# = v cc 0.3 v, wp# = v ih 0.2 5 a i cc4 v cc reset current (note 3) reset# = v ss 0.3 v, wp# = v ih 0.2 5 a i cc5 automatic sleep mode (notes 3, 5) v ih = v cc 0.3 v; v il = v ss 0.3 v, wp# = v ih 0.2 5 a v il input low voltage (note 6) ?0.5 0.8 v v ih input high voltage (note 6) 0.7 x v cc v cc + 0.3 v v hh voltage for acc program acceleration v cc = 3.0 v 10% 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0 v 10% 8.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage (note 7) i oh = ?2.0 ma, v cc = v cc min 0.85 x v io v v oh2 i oh = ?100 a, v cc = v cc min v io ?0.4 v v lko low v cc lock-out voltage (note 7) 2.3 2.5 v
39 am29lv641g june 14, 2005 advance information dc characteristics zero-power flash n ote: addresses are switching at 1 mhz figure 10. i cc1 current vs. time (showing ac tive and automatic sleep currents) 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 10 8 2 0 12345 frequency in mhz supply current in ma n ote: t = 25 c figure 11. typical i cc1 vs. frequency 4 6 12 2.7 v 3.6 v
june 14, 2005 am29lv641g 40 advance information test conditions table 12. test specifications note: if v io < v cc , the reference level is 0.5 v io . key to switching waveforms 2.7 k c l 6.2 k 3.3 v device under te s t n ote: diodes are in3064 or equivalent figure 12. test setup test condition 55r 70r unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels (see note) 1.5 v output timing measurement reference levels 0.5 v io v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 0.5 v io v output measurement level input n ote: if v io < v cc , the input measurement reference level is 0.5 v io . figure 13. input waveforms and measurement levels
41 am29lv641g june 14, 2005 advance information ac characteristics read-only operations notes: 1. not 100% tested. 2. see figure 12 and table 12 for test specifications. parameter description test setup speed options jedec std. 55r 70 unit t avav t rc read cycle time (note 1) min 55 70 ns t avqv t acc address to output delay ce#, oe# = v il max 55 70 ns t elqv t ce chip enable to output delay oe# = v il max 55 70 ns t glqv t oe output enable to output delay max 30 ns t ehqz t df chip enable to output high z (note 1) max 16 ns t ghqz t df output enable to output high z (note 1) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh reset# t df figure 14. read operation timings
june 14, 2005 am29lv641g 42 advance information ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s reset# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp figure 15. reset timings
43 am29lv641g june 14, 2005 advance information ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter speed options jedec std. description 55r 70 unit t avav t wc write cycle time (note 1) min 55 70 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 40 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 40 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 30 ns t whdl t wph write pulse width high min 25 ns t whwh1 t whwh1 word programming operation (note 2) typ 7 s t whwh1 t whwh1 accelerated word programming operation (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.6 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s
june 14, 2005 am29lv641g 44 advance information ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) t ch pa n otes: 1 . pa = program address, pd = program data, d out is the true data at the program address. il lustration shows device in word mode. figure 16. program operation timings acc t vhh v hh v il or v ih v il or v ih t vhh figure 17. accelerated program timing diagram
45 am29lv641g june 14, 2005 advance information ac characteristics oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status?. 2. these waveforms are for the word mode. figure 18. chip/sector erase operation timings
june 14, 2005 am29lv641g 46 advance information ac characteristics we# ce# oe# high z t oe high z dq7 dq6?dq0 complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc n ote: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data r ead cycle. figure 19. data# polling timings (during embedded algorithms)
47 am29lv641g june 14, 2005 advance information ac characteristics oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status n ote: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status r ead cycle, and array data read cycle figure 20. toggle bit timings (during embedded algorithms) n ote: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to togg le d q2 and dq6. figure 21. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
june 14, 2005 am29lv641g 48 advance information ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# t vidr t rsp program or erase command sequence figure 22. temporary sector group unprotect timing diagram
49 am29lv641g june 14, 2005 advance information ac characteristics sector group protect: 150 s, sector group unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect or unprotect verify v id v ih * for sector group protect, a6 = 0, a1 = 1, a0 = 0. for sector group unprotect, a6 = 1, a1 = 1, a0 = 0. figure 23. sector group protect and unprotect timing diagram
june 14, 2005 am29lv641g 50 advance information ac characteristics alternate ce# controlled erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter speed options jedec std description 55r 70 unit t avav t wc write cycle time (note 1) min 55 70 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 40 ns t dveh t ds data setup time min 40 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 word programming operation (note 2) typ 7 s t whwh1 t whwh1 accelerated word programming operation (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.6 sec
51 am29lv641g june 14, 2005 advance information ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy n otes: 1 . figure indicates last two bus cycles of a program or erase operation. 2 . pa = program address, sa = sector address, pd = program data. 3 . dq7# is the complement of the data written to the device. d out is the data written to the device. 4 . waveforms are for the word mode. figure 24. alternate ce# controlled write (erase/program ) operation timings
june 14, 2005 am29lv641g 52 advance information erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90 c, v cc = 3.0 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most words progra m faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bits are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 10 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 1,000,000 cycles. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. tsop & fbga pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 0.6 4 sec excludes 00h programming prior to erasure (note 4) chip erase time 50 sec word program time 7 210 s excludes system level overhead (note 5) accelerated word program time 4 120 s chip program time (note 3) 18 54 sec description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 fine-pitch bga 4.2 5.0 c out output capacitance v out = 0 tsop 8.5 12 fine-pitch bga 5.4 6.5 c in2 control pin capacitance v in = 0 tsop 7.5 9 fine-pitch bga 3.9 4.7 parameter description test conditions min unit minimum pattern data retention time 150 c 10 years 125 c 20 years
53 am29lv641g june 14, 2005 advance information physical dimensions fbe063?63-ball fine-pitch ball grid array (fbga) 11 x 12 mm package dwg rev af; 10/99
54 am29lv641g june 14, 2005 advance information physical dimensions laa064?64-ball fortified ball grid array (fortified bga) 13 x 11 mm package
june 14, 2005 am29lv641g 55 advance information physical dimensions ts 048?48-pin standard tsop ) note: for reference only. bsc is an ansi standard for basic space centering. dwg rev aa; 10/99
56 am29lv641g june 14, 2005 advance information revision summary revision a (august 9, 2002) initial release. revision a+1 (august 28, 2002) ordering information corrected order numbers and package markings. added marking convention explanation about en- hanced-v io markings. revision a+2 (october 18, 2002) global added 55r speed grade and removed 90 and 100 speed grade throughout datasheet. connection diagram removed the 56?pin ssop package diagram. special package handling instructions modified wording. ordering information changed the vio for 55r to equal 3.0 v?3.6 v and added 55 ns to valid combinations table. customer lockable: secsi sector not programmed or protected at the factory. added second bullet, secsi sector-protect verify text and figure 3. common flash memory interface (cfi) changed wording in last sentence of third paragraph from, ?...the autoselect mode.? to ?...reading array data.? changed cfi website address. command definitions changed wording in last sentence of first paragraph from, ?...resets the device to reading array data.? to ...?may place the device to an unknown state. a reset command is then required to return the device to read- ing array data.? tsop pin capacitance added fine-pitch bga capacitance. revision a+3 (june 14, 2005) cover page / title page added spansion eol cover page and eol disclaimer to amd title page. trademarks copyright ? 2001 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are r egistered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification pur poses only and may be trademarks of their respective companies .

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